Typically, a computer system includes a number of integrated circuits that communicate with one another to perform system applications. Often, the computer system includes one or more host controllers and one or more electronic subsystem assemblies, such as a dual in-line memory module (DIMM), a graphics card, an audio card, a facsimile card, and a modem card. To perform system functions, the host controller(s) and subsystem assemblies communicate via communication links, such as serial communication links and parallel communication links.
Typically, serial communication link protocols allow only one memory controller to access the devices on the serial channel. The memory controller is referred to as a channel master and the devices on the serial channel are referred to as channel slaves. As most servers have multiple processor sockets, the memory controller can be one external component that is accessed by the multiple processing units. This approach adds latency due to the front side bus connecting the memory controller to the processing units.
If a memory controller is integrated into a processing unit, the unit has direct access to only a part of the memory, namely the memory directly connected. If the memory connected to the other memory controller has to be accessed, the access comes with added latency. Some companies are working on switch fabrics that allow different memory controllers to access the whole memory space, which means small additional latency but increased cost and complexity.
Another solution includes a serial bus with two master memory controllers. Usually, busses which allow two master memory controllers, such as HyperTransport™, have internal queues which allow the reordering and prioritization of data packets. These queues increase latency and are not suitable for a memory interface whose performance depends heavily on decreased latency.
For these and other reasons there is a need for the present invention.